The present invention relates to communications in linear optical array chips.
Linear optical arrays consisting of multiple sensor chips and having digital I/O need a method of communicating with each chip in the array. Since there may be many chips in an array, it is preferable (consistent with bandwidth requirements) to use serial I/O in order to reduce the number of lines used for communication between the sensor chips and the control circuitry. It is also desirable to further reduce pin count and circuitry by using some type of addressing scheme, and to multiplex several serial I/O lines into common I/O pins in the control chip. This can be accomplished by using separate address decoding and chip select pins, or by embedding address information in the serial control stream. Embedding the chip address in the serial control stream in turn requires each chip connect to a serial I/O to have a unique address. A problem is how to establish the address of each chip in an array.
The present application discloses a communication and addressing technique in optical linear array chips whereby no chip select pins and associated decoding are required. Additionally, no pin programming or external hardware is required to establish addresses. The solution uses a tri-state output for the serial digital outputs of the chips in the array. A single line accommodating serial digital input data connects to all chips in a parallel fashion. The daisy-chain configuration is used to establish unique addresses for each chip in the array so that no external chip select decoding or pin programming is required. The innovative architecture offers addressing of optical sensor chips, and automatic address resolution among multi-chip arrays. Therefore, since chip addresses are determinative, communications to the sensor chips may be in the format of a general broadcast to all chips, or perhaps directed commands to specific chips. This permits array control circuitry to use a single serial input line and a single serial output line for communicating with all chips in an array. Another variation is to use odd and even address recognition. This permits all respective devices designated odd or even to respond to a command simultaneously. Furthermore, the output pins of the chips in the array can be tied together in pairs and respond to commands directed to odd or even addresses. This can be accomplished by recognizing addresses greater than some arbitrary number as either odd or even addresses. By using stop bits and start bits for framing the information to and from the devices, problems with timing are removed. Therefore, communication with individual chips within a multi-chip array with a single serial input may require only half as many serial outputs.
Advantages of the disclosed methods and structures include minimizing hardware and thus pin counts.